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MC10EP142, MC100EP142 3.3 V / 5 V ECL 9-Bit Shift Register
The MC10EP/100EP142 is a 9-bit shift register, designed with byte-parity applications in mind. The MC10/100EP142 is capable of performing serial/parallel data into serial/parallel out and shifting in only one direction. The nine inputs D0 - D8 accept parallel input data, while S-IN accepts serial input data. The QT0:87 outputs do not need to be terminated for the shift operation to function. To minimize power, any Q output not used should be left unterminated. The SEL (Select) input pin is used to switch between the two modes of operation - SHIFT and LOAD. The shift direction is from Bit 0 to Bit 8. Input data is accepted by the registers a set-up time before the positive going edge of CLK0 or CLK1; shifting is also accomplished on the positive clock edge. A HIGH on the Master Reset pin (MR) asynchronously resets all the registers to zero, overriding CLK0 and CLK1 inputs. The 100 Series contains temperature compensation.
Features http://onsemi.com MARKING DIAGRAM*
LQFP-32 FA SUFFIX CASE 873A
MCxxx EP142 AWLYYWWG 32 1
1
* * * * * * * * *
Shift Frequency >2.8 GHz (Typical) 9-Bit for Byte-Parity Applications Asynchronous Master Reset Dual Clocks PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V Open Input Default State Safety Clamp on Inputs Pb-Free Packages are Available
1
32
QFN32 MN SUFFIX CASE 488AM
MCxxx EP142 AWLYYWWG G
xxx = 10 or 100 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2006
November, 2006 - Rev. 16
1
Publication Order Number: MC10EP142/D
MC10EP142, MC100EP142
VCC Q8 Q7 Q7 Q6 Q5 D7 D8 VCC
17 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8
Q8
Q7
Q7
Q6
19
24
23
22
21
20
D6 D5 D4 VEE D3 D2 D1 VCC
24 25 26 27 28 29 30 31 32 1
23
22
21
20
19
18
17 16 15 14 VEE Q4 Q3 VCC Q2 Q1 Q0 MR
Q5
18
D7
D8
D6 D5 D4 VEE D3 D2 D1 VCC
25 26 27 28 29 30 31 32
VEE Q4 Q3 VCC Q2 Q1 Q0 MR
MC10EP142 MC100EP142
13 12 11 10 9
Exposed Pad (EP)
2
3
4
5
6
7
8
CLK0
CLK0
CLK1
S-IN
D0
S-IN
CLK1
CLK0
CLK0
CLK1
S-IN
S-IN
D0
CLK1
Figure 1. Pinout: LQFP-32 (Top View)
SEL
Figure 2. Pinout: QFN-32 (Top View)
Table 1. PIN DESCRIPTION
Pin 1,23,24,25,26, 27,29,30,31 2 3 4 5 6 7 8 9 10,11,12,14,1 5,18,19,22 13,17,32 16,28 20 21 Name D[0:8] S-IN S-IN CLK0 CLK0 CLK1 CLK1 SEL MR Q0,Q1,Q2,Q3, Q4,Q5,Q6,Q8 VCC VEE Q7 Q7 I/O ECL Input ECL Input ECL Input ECL Input ECL Input ECL Input ECL Input ECL Input ECL Input ECL Output - - ECL Output ECL Output Default State Low Low High Low High Low High Low Low - - - - - Description Single-Ended Parallel Data Inputs [0:8]. Internal 75 kW to VEE. Noninverted Differential Serial Input. Internal 75 kW to VEE. Inverted Differential Serial Input. Internal 75 kW to VEE and 36.5 kW to VCC. Noninverted Differential CLK0 Input. Internal 75 kW to VEE. Inverted Differential CLK0B Input. Internal 75 kW to VEE and 36.5 kW to VCC. Noninverted Differential CLK1 Input. Internal 75 kW to VEE. Inverted Differential CLK1B Input. Internal 75 kW to VEE and 36.5 kW to VCC. Single-Ended Select Logic Input. Internal 75 kW to VEE. Single-Ended Master Reset Logic Input. Internal 75 kW to VEE. Single-Ended parallel Data outputs [0,1,2,3,4,5,6,8]. Typically Terminated with 50 W to VTT = VCC - 2 V. Positive supply Voltage. All VCC Pins must be Externally Connected to Power Supply to Guarantee Proper Operation. Negative supply Voltage. All VEE Pins must be Externally connected to Power Supply to Guarantee Proper Operation. Noninverted Differential parallel/Serial Data Output 7. Typically Terminated with 50 W to VTT = VCC - 2 V. Inverted Differential parallel/Serial Data Output 7. Typically Terminated with 50 W to VTT = VCC - 2 V.
1. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
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SEL
MC10EP142, MC100EP142
Table 2. TRUTH TABLE
Function (Note 2) Load Shift SEL L H H Reset X S-IN X L H X MR L L L H CLK0 Z Z Z Z CLK1 Z Z Z Z Q0 D0 L H L Q1 D1 Q0 Q0 L Q2 D2 Q1 Q1 L Q3 D3 Q2 Q2 L Q4 D4 Q3 Q3 L Q5 D5 Q4 Q4 L Q6 D6 Q5 Q5 L Q7 D7 Q6 Q6 L Q8 D8 Q7 Q7 L Q9 D9 Q8 Q8 L
2. All Load and Shift functions are accomplished on the positive edge of CLK0 or CLK1.
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MC10EP142, MC100EP142
S-IN R2 S-IN D0 R1 R1 R1 1 0 D Q Q0
D1
1 0 R1
D
Q
Q1
D2
R1
1 0
D
Q
Q2
D3
R1
1 0
D
Q
Q3
D4
R1
1 0
D
Q
Q4
D5
R1
1 0
D
Q
Q5
1 D6 R1 0
D
Q
Q6
D7
R1
1 0
D
Q Q
Q7 Q7
D8
R1 SEL MR R1 R1
1 0
D
Q
Q8
CLK0 CLK0 CLK1 CLK1 R2 R1 R2 R1
VCC VEE
R1
Figure 3. Logic Diagram http://onsemi.com
4
MC10EP142, MC100EP142
Table 3. ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection (R1) (R2) Human Body Model Machine Model Charged Device Model LQFP QFN Oxygen Index: 28 to 34 Value 75 kW 37.5 kW > 2 kV > 100 V > 2 kV Level 2 Level 1 UL-94 V-0 @ 0.125 in 405 Devices
Moisture Sensitivity (Note 3) Flammability Rating Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, refer to Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol VCC VEE VI Iout TA Tstg qJA qJC qJA qJC Tsol Parameter Positive Power Supply Negative Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder Pb Pb-Free 0 lfpm 500 lfpm Standard Board 0 lfpm 500 lfpm 2S2P v3 sec @ 248C v3 sec @ 260C LQFP-32 LQFP-32 LQFP-32 QFN-32 QFN-32 QFN-32 Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI v VCC VI w VEE Condition 2 Rating 8 -8 6 -6 50 100 -40 to +85 -65 to +150 80 55 12 to 17 31 27 12 265 265 Unit V V V mA C C C/W C/W C/W C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
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MC10EP142, MC100EP142
Table 5. 10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 4)
-40C Symbol IEE VOH VOL VIH VIL VIHCMR Characteristic Negative Power Supply Current Output HIGH Voltage (Note 5) Output LOW Voltage (Note 5) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 6) Input HIGH Current (@ VIH) Input LOW Current (@ VIL) CLK0, CLK1, D, S-IN CLK0, CLK1, S-IN 0.5 -150 Min 105 2165 1365 2090 1365 2.0 Typ 125 2290 1490 Max 145 2415 1615 2415 1690 3.3 Min 105 2230 1430 2155 1460 2.0 25C Typ 125 2355 1555 Max 145 2480 1680 2480 1755 3.3 Min 105 2290 1490 2215 1490 2.0 85C Typ 125 2415 1615 Max 145 2540 1740 2540 1815 3.3 Unit mA mV mV mV mV V
IIH IIL
150 0.5 -150
150 0.5 -150
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V. 5. All loading with 50 W to VCC - 2.0 V. 6. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
Table 6. 10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 7)
-40C Symbol IEE VOH VOL VIH VIL VIHCMR Characteristic Negative Power Supply Current (Note 8) Output HIGH Voltage (Note 9) Output LOW Voltage (Note 9) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 10) Input HIGH Current (@ VIH) Input LOW Current (@ VIL) CLK0, CLK1, D, S-IN CLK0, CLK1, S-IN 0.5 -150 Min 105 3865 3065 3790 3065 2.0 Typ 125 3990 3190 Max 145 4115 3315 4115 3390 5.0 Min 105 3930 3130 3855 3130 2.0 25C Typ 125 4055 3255 Max 145 4180 3380 4180 3455 5.0 Min 105 3990 3190 3915 3190 2.0 85C Typ 125 4115 3315 Max 145 4240 3440 4240 3515 5.0 Unit mA mV mV mV mV V
IIH IIL
150 0.5 -150
150 0.5 -150
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V. 8. Required 500 lfpm air flow when using +5 V power supply. For (VCC - VEE) >3.3 V, 5 W to 10 W in line with VEE required for maximum thermal protection at elevated temperatures. Recommend VCC - VEE operation at 3.3 V. 9. All loading with 50 W to VCC - 2.0 V. 10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP142, MC100EP142
Table 7. 10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 11)
-40C Symbol IEE VOH VOL VIH VIL VIHCMR Characteristic Negative Power Supply Current (Note 12) Output HIGH Voltage (Note 13) Output LOW Voltage (Note 13) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 14) Input HIGH Current (@ VIH) Input LOW Current (@ VIL) CLK0, CLK1, D, S-IN CLK0, CLK1, S-IN 0.5 -150 Min 105 -1135 -1935 -1210 -1935 VEE+2.0 Typ 125 -1010 -1810 Max 145 -885 -1685 -885 -1610 0.0 Min 105 -1070 -1870 -1145 -1870 VEE+2.0 25C Typ 125 -945 -1745 Max 145 -820 -1620 -820 -1545 0.0 Min 105 -1010 -1810 -1085 -1810 VEE+2.0 85C Typ 125 -885 -1685 Max 145 -760 -1560 -760 -1485 0.0 Unit mA mV mV mV mV V
IIH IIL
150 0.5 -150
150 0.5 -150
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. Input and output parameters vary 1:1 with VCC. 12. Required 500 lfpm air flow when using -5 V power supply. For (VCC - VEE) >3.3 V, 5 W to 10 W in line with VEE required for maximum thermal protection at elevated temperatures. Recommend VCC-VEE operation at 3.3 V. 13. All loading with 50 W to VCC - 2.0 V. 14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
Table 8. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 15)
-40C Symbol IEE VOH VOL VIH VIL VIHCMR Characteristic Negative Power Supply Current Output HIGH Voltage (Note 16) Output LOW Voltage (Note 16) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 17) Input HIGH Current (@ VIH) Input LOW Current (@ VIL) CLK0, CLK1, D, S-IN CLK0, CLK1, S-IN 0.5 -150 Min 105 2155 1355 2075 1355 2.0 Typ 125 2280 1480 Max 145 2405 1605 2420 1675 3.3 Min 105 2155 1355 2075 1355 2.0 25C Typ 130 2280 1480 Max 150 2405 1605 2420 1675 3.3 Min 105 2155 1355 2075 1355 2.0 85C Typ 130 2280 1480 Max 150 2405 1605 2420 1675 3.3 Unit mA mV mV mV mV V
IIH IIL
150 0.5 -150
150 0.5 -150
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 15. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V. 16. All loading with 50 W to VCC - 2.0 V. 17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP142, MC100EP142
Table 9. 100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 18)
-40C Symbol IEE VOH VOL VIH VIL VIHCMR Characteristic Negative Power Supply Current (Note 19) Output HIGH Voltage (Note 20) Output LOW Voltage (Note 20) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 21) Input HIGH Current (@ VIH) Input LOW Current (@ VIL) CLK0, CLK1, D, S-IN CLK0, CLK1, S-IN 0.5 -150 Min 105 3855 3055 3775 3055 2.0 Typ 125 3980 3180 Max 145 4105 3305 4120 3375 5.0 Min 105 3855 3055 3775 3055 2.0 25C Typ 130 3980 3180 Max 150 4105 3305 4120 3375 5.0 Min 105 3855 3055 3775 3055 2.0 85C Typ 130 3980 3180 Max 150 4105 3305 4120 3375 5.0 Unit mA mV mV mV mV V
IIH IIL
150 0.5 -150
150 0.5 -150
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 18. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V. 19. Required 500 lfpm air flow when using +5 V power supply. For (VCC - VEE) >3.3 V, 5 W to 10 W in line with VEE required for maximum thermal protection at elevated temperatures. Recommend VCC-VEE operation at 3.3 V. 20. All loading with 50 W to VCC - 2.0 V. 21. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
Table 10. 100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 22)
-40C Symbol IEE VOH VOL VIH VIL VIHCMR Characteristic Negative Power Supply Current (Note 23) Output HIGH Voltage (Note 24) Output LOW Voltage (Note 24) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 25) Input HIGH Current (@ VIH) Input LOW Current (@ VIL) CLK0, CLK1, D, S-IN CLK0, CLK1, S-IN 0.5 -150 Min 105 -1145 -1945 -1225 -1945 VEE+2.0 Typ 125 -1020 -1820 Max 145 -895 -1695 -880 -1625 0.0 Min 105 -1145 -1945 -1225 -1945 VEE+2.0 25C Typ 130 -1020 -1820 Max 150 -895 -1695 -880 -1625 0.0 Min 105 -1145 -1945 -1225 -1945 VEE+2.0 85C Typ 130 -1020 -1820 Max 150 -895 -1695 -880 -1625 0.0 Unit mA mV mV mV mV V
IIH IIL
150 0.5 -150
150 0.5 -150
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 22. Input and output parameters vary 1:1 with VCC. 23. Required 500 lfpm air flow when using -5 V power supply. For (VCC - VEE) >3.3 V, 5 W to 10 W in line with VEE required for maximum thermal protection at elevated temperatures. Recommend VCC-VEE operation at 3.3 V. 24. All loading with 50 W to VCC - 2.0 V. 25. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP142, MC100EP142
Table 11. AC CHARACTERISTICS VCC = 3.0 V to 5.5 V; VEE = 0.0 V or VCC = 0.0 V; VEE = -3.0 V to -5.5 V (Note 26)
-40C Symbol fSHIFT tPLH, tPHL ts Characteristic Maximum Shift Frequency Propagation Delay to Output CLKx MR D SEL th Hold Time D SEL tRR tpw tSKEW tJITTER Vinpp tr, tf Reset Recovery Time Minimum Pulse Width Within-Device Skew (Note 27) Duty Cycle Skew (Note 28) Random Clock Jitter (Figure 4) Input Voltage Swing/Sensitivity (Differential Configuration) Rise/Fall Times @ 50 MHz (20 - 80%) 150 110 Q, Q 50 5.0 1 800 180 100 20 2 1200 250 150 125 100 50 50 -50 100 50 50 -50 800 200 50 5.0 1 800 190 100 20 2 1200 275 150 150 50 5.0 1 800 215 100 20 2 1200 300 100 50 50 -50 ps ps ps ps mV ps 500 500 50 100 625 625 -50 50 750 750 550 550 50 100 Min Typ Max Min 25C Typ 2.8 675 675 -50 50 800 800 575 575 50 100 700 700 -50 50 ps 825 825 Max Min 85C Typ Max Unit GHz ps
Setup Time
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 26. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC - 2.0 V. 27. Within-device skew is defined as identical transitions on similar paths through a device. 28. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point of the outputs. 900 800 Output Voltage Amplitude (mV) 700 600 500 400 300 200 9 JITTER OUT ps (RMS) 8 7 6 5 4 3 2 1 4000 5000 6000
EEEEEEEEE EEEEEEEEE
0 0 1000 2000
100
3000
INPUT FREQUENCY (MHz)
Figure 4. Output Voltage Amplitude / RMS Jitter vs. Input Frequency at Ambient Temperature (Typical)
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EE EE EE
MC10EP142, MC100EP142
CLK VINPP = VIH(CLK) - VIL(CLK) CLK Q VOUTPP = VOH(Q) - VOL(Q) Q tPHL tPLH
Figure 5. AC Reference Measurement
Q Driver Device Q
Zo = 50 W
D Receiver Device
Zo = 50 W 50 W 50 W
D
VTT VTT = VCC - 2.0 V
Figure 6. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
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MC10EP142, MC100EP142
ORDERING INFORMATION
Device MC10EP142FA MC10EP142FAG MC10EP142FAR2 MC10EP142FAR2G MC10EP142MNG MC10EP142MNR4G MC100EP142FA MC100EP142FAG MC100EP142FAR2 MC100EP142FAR2G MC100EP142MNG MC100EP142MNR4G Package LQFP-32 LQFP-32 (Pb-Free) LQFP-32 LQFP-32 (Pb-Free) QFN-32 (Pb-Free) QFN-32 (Pb-Free) LQFP-32 LQFP-32 (Pb-Free) LQFP-32 LQFP-32 (Pb-Free) QFN-32 (Pb-Free) QFN-32 (Pb-Free) Shipping 250 Units / Tray 250 Units / Tray 2000 / Tape & Reel 2000 / Tape & Reel 74 Units / Rail 1000 / Tape & Reel 250 Units / Tray 250 Units / Tray 2000 / Tape & Reel 2000 / Tape & Reel 74 Units / Rail 1000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPSt I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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MC10EP142, MC100EP142
PACKAGE DIMENSIONS
32 LEAD LQFP CASE 873A-02 ISSUE C
32
A1
A
25
4X
0.20 (0.008) AB T-U Z
1
-T- B B1
8
-U- V V1
AE P AE
17
DETAIL Y
BASE METAL
N 9 -Z- S
8X M_
S1
R
J
G -AB-
SEATING PLANE
DETAIL AD CE
SECTION AE-AE
-AC- 0.10 (0.004) AC 0.250 (0.010) H W X DETAIL AD K Q_
GAUGE PLANE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION.
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.450 0.750 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF
INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.018 0.030 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
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0.20 (0.008)
0.20 (0.008) AC T-U Z
F
EE EE EE
9
D
M
4X
AC T-U Z
DETAIL Y
-T-, -U-, -Z-
MC10EP142, MC100EP142
PACKAGE DIMENSIONS
QFN32 5*5*1 0.5 P CASE 488AM-01 ISSUE O
D A B
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN NOM MAX 0.800 0.900 1.000 0.000 0.025 0.050 0.200 REF 0.180 0.250 0.300 5.00 BSC 2.950 3.100 3.250 5.00 BSC 2.950 3.100 3.250 0.500 BSC 0.200 --- --- 0.300 0.400 0.500
2X 2X
0.15 C 0.15 C 0.10 C
32 X
0.08 C L
32 X 9 8
1
b 0.10 C A B
32 X
0.05 C BOTTOM VIEW
32 X
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC)
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
EE
TOP VIEW SIDE VIEW D2
16 17 32 25
PIN ONE LOCATION
E
(A3) A A1 C
EXPOSED PAD 32 X SEATING PLANE
DIM A A1 A3 b D D2 E E2 e K L
K
SOLDERING FOOTPRINT*
5.30 3.20 0.63
32 X
E2
24
e
3.20
5.30
0.28
0.50 PITCH
28 X
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
13
MC10EP142/D

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